Semiconductor processing typically includes forming a plurality of layers over a substrate such as a monocrystalline silicon wafer. During processing, the layers are typically etched into and formed to include various integrated circuit components such as conductive lines, transistor gate lines, resistors, capacitors, and the like. During processing, anomalies in the various layers can occur which can adversely affect the finished device. Yet, it is often not possible to detect such anomalies until a finished device is electronically tested. Anomalies or defects can be caused by mechanical and/or chemical sources.
For example, sometimes during the handling of a wafer in process, the wafer handling apparatus can cause a physical surface defect which can adversely impact a finished device. Alternately, some aspects of chemical processing can adversely affect various layers of the wafer. If a number of such devices are contemporaneously fabricated, anomalies or defects which present themselves early in the processing can have an effect which promulgates its way through all of the devices. Yet, early detection of such anomalies could allow for preventative measures to be taken. An exemplary layer which can be adversely affected during processing by such anomalies or defects is a gate oxide layer for a transistor. Accordingly, it would be desirable to be able to determine the presence of anomalies or defects, midstream during the processing flow.
This invention arose out of concerns associated with providing improved methods of semiconductor processing, and in particular, improved methods of semiconductor defect detection.